1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to an improved method for making process films comprised of silicon nitride.
2. Description of the Related Art
In the manufacture of semiconductor devices, process films comprised of silicon nitride are formed at various points during the manufacturing process. By way of example, nitride films are formed in connection with the formation of nitride spacers positioned adjacent the gate conductor of a transistor. One illustrative technique for forming such spacers is depicted in FIGS. 1 and 2 of the attached drawings.
As shown in FIG. 1, a gate stack 12 comprised of a gate conductor 16 and a gate dielectric 14 are formed above a surface 11 of a semiconducting substrate 10. The gate dielectric 14 and the gate conductor 16 are typically made by forming process layers comprised of the appropriate materials above the surface 11 of the substrate 10, and patterning those layers by performing one or more etching processes to define the gate stack 12. Thereafter, the substrate 10 is subjected to a low energy ion implantation process to form lightly doped regions 20 in the substrate 10. Next, a layer 18 of silicon nitride is typically formed above the surface 11 of the substrate 10 and above the gate stack 12 by one or more processes, such as a plasma enhanced chemical vapor deposition ("PECVD") process. Thereafter, the device is subjected to one or more anisotropic etching processes to define sidewall spacers 22 comprised of silicon nitride, as shown in FIG. 2. An additional ion implantation process is then performed to complete the formation of the source/drain regions 24 having the familiar lightly doped drain ("LDD") structure. The fabrication of the transistor is completed by forming appropriate metal contacts through various openings in the layers of dielectric material positioned above the device.
Although there are existing techniques for forming the layer 18 comprised of silicon nitride, the layers resulting from such known techniques or processes exhibit many problems that are detrimental to device performance and integrity. As is well known to those skilled in the art, given the continuing drive to reduce the size of the transistors and increase the operating speed of the transistors, it is imperative that all aspects of the semiconductor device, including the formation of the nitride spacers 22, must be optimized to produce integrated circuit devices of the speed and integrity required by modern electronic devices.
Once problem associated with using known techniques for forming silicon nitride layers is that such techniques produce unacceptable variations in the thickness of the deposited layer. For example, using known processes, a deposited layer of silicon nitride may vary in thickness by as much as .+-.5%, e.g., a silicon nitride layer of a nominal thickness of 1000 .ANG. may vary by .+-.50 .ANG.. Such variations in the thickness of the nitride layers formed using known techniques and processes may lead to unacceptable results and decreased transistor performance. For example, if the width of the silicon nitride spacer 22 is 5% wider than anticipated by the transistor designers, adverse impacts on the operating performance of the transistor may occur, i.e., the location of the dopant added during the second implant step may be varied so as to reduce transistor performance below acceptable limits.
Another problem associated with known processes and techniques for forming silicon nitride layers is that the step coverage of the nitride layer as it is formed over a structure, or step, is less than desired. By way of background, step coverage is an expression of the minimum thickness of a process layer as it passes over a step, e.g., a gate stack, as compared to the nominal thickness of the deposited layer on a horizontal surface, expressed as a percentage. Ideally, the thickness of the deposited layer of nitride is uniform as it is formed over such a step. However, as a practical matter, there is ordinarily some thinning of the process layer as it is formed over various steps on the topography of the semiconductor device. Poor step coverage can lead to many problems, among which is a lack of thickness control and nonuniformity of not only the layer under consideration, but layers formed subsequent to the formation of the nitride layer.
Another problem encountered with nitride layers that have been formed using prior art processes is that there may be problems in measuring the thickness of the nitride layer formed over a preexisting layer of silicon dioxide. Part of the problem is due to the relatively low density of the silicon nitride layer formed using known techniques and processes. For example, problems are sometimes encountered using a metrology tool known as an Optiprobe due, in part, to the lower density of silicon nitride layers formed using known processes and techniques.
Yet another problem encountered with the formation of nitride layers using existing PECVD processes is the relatively large amount of power used to form such nitride films. In general, the higher power usage during the formation of such nitride layers may lead to problems such as shifting of the threshold voltage of the resulting semiconductor device.
Therefore, it is desirable to have a method that reduces the amount of power used to form such nitride films in modern semiconductor devices.
The present invention is directed to solving, or at least reducing, some or all of the aforementioned problems.